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MRF89XA
3.12 Initialization
Certain control register values must be initialized for
basic operations of the MRF89XA. These values differ
from the POR values and provide improved operational
parameters. These settings are normally made once
after a Reset. After initialization, the other features of
the MRF89XA device can be configured based on the
a) Enable Passive Filter with value as set in
step 11.
b) Set f c and f o .
c) Enable SYNC and Set SYNC Word, Size,
Length and Tolerance.
d) Set configuration bytes for OOK Threshold
from OOKCREG
application. Accessing a register is implied as a com-
mand to the MRF89XA device through the SPI port.
The steps to initialize the MRF89XA using the control
registers are as follows:
1. In the GCONREG register:
a) Set the Chip Mode (CMOD<2:0>), Fre-
quency Band (FBS<1:0>) and VCO Trim
(VCOT<1:0>) bits.
b) Program the Frequency band.
c) Set the Trim bits to appropriately tune in the
VCO.
2. In the DMODREG register:
a) Select the Modulation Type using the MOD-
SEL<1:0> bits.
b) Enable DATA mode for Transmission using
the DMODE0 and DMODE1 bits.
c) Select gain for IF chain using the
IFGAIN<1:0> bits.
d) In the FDEVREG register, program the Fre-
quency Deviation bits (FDVAL<7:0>).
12.
13.
14.
15.
16.
In the SYNCREG register, set
SYNCWSZ<1:0> = 11 for 32-bit SYNC word.
Configure TX parameters:
a) Change or Reset f c .
b) In the TXCONREG register, enable TX and
its transmit power using the
TXIPOLFV<3:0> and TXOPVAL<2:0> bits.
In the CLKOUTREG register, configure the
Clock Settings using the CLKOCNTRL and
CLKOFREQ<4:0> bits.
Configure the Packet Frame parameters in the
PLOADREG, NADDSREG, PKTCREG and
FCRCREG registers:
a) Enable Manchester Encoding
b) Set packet format and length of the packet
c) Set Node local address
d) Program preamble variables
e) Configure CRC parameters
f) Enable Address Filtering
In the FCRCREG register, enable FIFO write
3. In the BRSREG register, program the Bit Rate
using the BRVAL<6:0> bits.
4. In the FLTHREG register, set the Floor Thresh-
old for OOK using the FTOVAL<7:0> bits.
5. In the FIFOCREG register, configure the FIFO
Size and FIFO Threshold using the FSIZE<1:0>
and FTINT<5:0> bits.
6. In the PACREG register, configure the Power
Amplifier Ramp Control using the PARC<1:0>
bits.
7. In the FTXRXIREG register:
a) Configure the RX interrupts for IRQ0 and
IRQ1 using the IRQ0RXS<1:0> and
IRQ1RXS<1:0> bits.
b) Configure the TX interrupts for IRQ1 using
the IRQ1TX bit.
8. In the FTPRIREG register:
a) Configure the TX interrupts for IRQ0 using
the IRQ0TXST bit.
b) Enable PLL Lock for interrupt on IRQ1
using the LENPLL bit.
9. In the RSTHIREG, program the RSSI Threshold
value for interrupt request using the
RTIVAL<7:0> bits.
10. In the FILCREG register, enable the Passive
Filter using the PASFILV<3:0> bits.
11. Configure RX parameters:
access using the FRWAXS bit.
Note 1: Program registers 0x00 - 0x1F with
appropriate settings. (General Configura-
tion Parameters, IRQ Parameters,
Packet Parameters).
2: Clear the PLL Lock flag by setting the
LSTSPLL bit (FTPRIREG 0x0E<1>) to
‘ 1 ’.
3: Program CMOD bits (GCONREG 0x00
<7:5>) to ‘0b010 Frequency Synthe-
sizer mode.
4: Verify the PLL lock flag through the LST-
SPLL bit (FTPRIREG 0x0E<1>). If LST-
SPLL = 1 , it implies that the MRF89XA is
ready to operate at the frequency indi-
cated by the Ri/Pi/Si register set.
5: Program the CMOD bits (GCONREG
0x00 <7:5>) to ‘0b001 Standby mode.
DS70622C-page 90
Preliminary
? 2010–2011 Microchip Technology Inc.
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